SH7706 Datasheet, PDF (421/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 14 Serial Communication Interface (SCI)
Bit Bit Name Initial Value R/W Description
5
TE
0
R/W Transmit Enable
Enables or disables the SCI serial transmitter.
0: Transmission disabled
Note: The TDRE in SCSSR is fixed to 1.
1: Transmission enabled
Note: Serial transmission starts when TDRE bit in
SCSSR is cleared to 0 after writing of transmit data
into the SCTDR. Specify the transmit format to the
SCSMR before setting TE to 1.
4
RE
0
R/W Receive Enable
Enables or disables the SCI serial receiver.
0: Reception disabled
Note: Clearing RE to 0 does not affect the receive
flags (RDRF, FER, PER, ORER). These flags retain
their previous values.
1: Reception enabled
Note: Serial reception starts when a start bit is
detected in the asynchronous mode, or synchronous
clock input is detected in the clock synchronous
mode. Specify the receive format to the SCSMR
before setting RE to 1.
Rev. 5.00 May 29, 2006 page 373 of 698
REJ09B0146-0500