SH7706 Datasheet, PDF (246/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 8 Bus State Controller (BSC)
Table 8.11 32-Bit External Device/Big Endian Access and Data Alignment
Operation
Byte access at 0
Byte access at 1
Byte access at 2
Byte access at 3
Word access at 0
Word access at 2
Longword access
at 0
D31 to
D24
Data
7 to 0
—
—
—
Data
15 to 8
—
Data
31 to 24
Data Bus
D23 to D15 to
D16
D8
—
—
Data
7 to 0
—
—
—
Data
7 to 0
—
Data —
7 to 0
—
Data
15 to 8
Data Data
23 to 16 15 to 8
D7 to
D0
—
—
—
Data
7 to 0
—
Data
7 to 0
Data
7 to 0
WE3,
DQMUU
Assert
Strobe Signals
WE2,
WE1,
DQMUL DQMLU
WE0,
DQMLL
Assert
Assert
Assert
Assert Assert
Assert Assert
Assert Assert Assert Assert
Table 8.12 16-Bit External Device/Big Endian Access and Data Alignment
Data Bus
Operation
D31 to D23 to D15 to D7 to
D24 D16 D8
D0
WE3,
DQMUU
Byte access at 0
——
Data
—
7 to 0
Byte access at 1
—
—
—
Data
7 to 0
Byte access at 2
—
—
Data
—
7 to 0
Byte access at 3
—
—
—
Data
7 to 0
Word access at 0
——
Data
Data
15 to 8 7 to 0
Word access at 2
——
Data
Data
15 to 8 7 to 0
Longword 1st
—
—
Data
Data
access
time at 0
31 to 24 23 to 16
at 0
2nd
—
—
Data
Data
time at 2
15 to 8 7 to 0
Strobe Signals
WE2,
DQMUL
WE1,
DQMLU
Assert
Assert
Assert
Assert
Assert
Assert
WE0,
DQMLL
Assert
Assert
Assert
Assert
Assert
Assert
Rev. 5.00 May 29, 2006 page 198 of 698
REJ09B0146-0500