SH7706 Datasheet, PDF (176/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 6 Interrupt Controller (INTC)
Bit Bit Name Initial Value R/W Description
5
IRQ21S 0
R/W IRQ2 Sense Select
4
IRQ20S 0
R/W Select whether the interrupt signal to the IRQ2 pin
is detected at the rising edge, at the falling edge, or
at low level.
00: An interrupt request is detected at IRQ2 input
falling edge
01: An interrupt request is detected at IRQ2 input
rising edge
10: An interrupt request is detected at IRQ2 input
low level
11: Reserved (Setting prohibited)
3
IRQ11S 0
R/W IRQ1 Sense Select
2
IRQ10S 0
R/W Select whether the interrupt signal to the IRQ1 pin
is detected at the rising edge, at the falling edge, or
at low level.
00: An interrupt request is detected at IRQ1 input
falling edge
01: An interrupt request is detected at IRQ1 input
rising edge
10: An interrupt request is detected at IRQ1 input
low level
11: Reserved (Setting prohibited)
1
IRQ01S 0
R/W IRQ0 Sense Select
0
IRQ00S 0
R/W Select whether the interrupt signal to the IRQ0 pin
is detected at the rising edge, at the falling edge, or
at low level.
00: An interrupt request is detected at IRQ0 input
falling edge
01: An interrupt request is detected at IRQ0 input
rising edge
10: An interrupt request is detected at IRQ0 input
low level
11: Reserved (Setting prohibited)
Rev. 5.00 May 29, 2006 page 128 of 698
REJ09B0146-0500