SH7706 Datasheet, PDF (297/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 8 Bus State Controller (BSC)
IRQOUT Pin Assertion Conditions:
• When a memory refresh request has been generated but the refresh cycle has not yet begun
• When an interrupt is generated with an interrupt request level higher than the setting of the
interrupt mask bits (I3 to I0) in the status register (SR). (This does not depend on the SR.BL
bit.)
8.5.9 Bus Pull-Up
With this LSI, address pin pull-up can be performed when the bus is released by setting the PULA
bit in BCR1 to 1. The address pins are pulled up for a 4-clock period after BACK is asserted.
Figure 8.40 shows the address pin pull-up timing. Similarly, data pin pull-up can be performed by
setting the PULD bit in BCR1 to 1. The data pins should be pulled up when the data bus is not in
use. The data pin pull-up timing for a read cycle is shown in figure 8.41, and the timing for a write
cycle in figure 8.42.
CKIO
A25 to A0
BACK
Pull-up
Hi-Z
Figure 8.40 Pins A25 to A0 Pull-Up Timing
Rev. 5.00 May 29, 2006 page 249 of 698
REJ09B0146-0500