SH7706 Datasheet, PDF (466/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 14 Serial Communication Interface (SCI)
14.6 Usage Note
Note the following points when using the SCI.
SCTDR Writing to and TDRE Flag: The TDRE bit in SCSSR is a status flag indicating loading
of transmit data from the SCTDR into the SCTSR. The SCI sets TDRE to 1 when it transfers data
from the SCTDR to the SCTSR. Data can be written to the SCTDR regardless of the TDRE bit
state. If new data is written in the SCTDR when TDRE is 0, however, the old data stored in the
SCTDR will be lost because the data has not yet been transferred to the SCTSR. Before writing
transmit data to the SCTDR, be sure to check that TDRE is set to 1.
Simultaneous Multiple Receive Errors: Table 14.13 indicates the state of the SCSSR status
flags when multiple receive errors occur simultaneously. When an overrun error occurs, the
SCRSR contents cannot be transferred to the SCRDR, so receive data is lost.
Table 14.13 SCSSR Status Flags and Transfer of Receive Data
Receive Error Status
SCSSR Status Flags
Receive Data Transfer
RDRF ORER FER PER SCRSR → SCRDR
Overrun error
1
1
00
X
Framing error
0
0
10
O
Parity error
0
0
01
O
Overrun error + framing error
1
1
10
X
Overrun error + parity error
1
1
01
X
Framing error + parity error
0
0
11
O
Overrun error + framing error + parity 1
1
11
X
error
Legend: X: Receive data is not transferred from SCRSR to SCRDR.
O: Receive data is transferred from SCRSR to SCRDR.
Break Detection and Processing: Break signals can be detected by reading the RxD0 pin directly
when a framing error (FER) is detected. In the break state, the input from the RxD0 pin consists of
all 0s, so FER is set and the parity error flag (PER) may also be set. In the break state, the SCI
receiver continues to operate, so if the FER bit is cleared to 0, it will be set to 1 again.
Sending a Break Signal: The TxD0 pin I/O condition and level can be determined by means of
the SCP0DT bit of the SCPDR and bits SCP0MD0 and SCP0MD1 of the SCPCR. These bits can
be used to send breaks. To send a break during serial transmission, clear the SCP0DT bit to 0
(designating low level), then clear the TE bit to 0 (halting transmission). When the TE bit is
Rev. 5.00 May 29, 2006 page 418 of 698
REJ09B0146-0500