SH7706 Datasheet, PDF (528/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
16.4.2 SCIF Interrupts
The SCIF has four interrupt sources: transmit-FIFO-data-empty (TXI), receive-error (ERI),
receive-data-full (RXI), and break (BRI).
Table 16.9 shows the interrupt sources and their order of priority. The interrupt sources are
enabled or disabled by means of the TIE and RIE bits in SCSCR2. A separate interrupt request is
sent to the interrupt controller for each of these interrupt sources.
When the TDFE flag in the SCSSR2 is set to 1, a TXI interrupt request is generated. The DMAC
can be activated and data transfer performed when this interrupt is generated. The TDFE flag is
cleared to 0 when data exceeding the number of transmit triggers is written to SCFTDR2 by the
DMAC, the TDFE flag is read as 1, then 0 is written to the TDFE flag.
When the RDF flag in SCSSR2 is set to 1, an RXI interrupt request is generated. The DMAC can
be activated and data transfer performed when the RDF flag in SCSSR2 is set to 1. The RDF flag
is cleared to 0 when SCFRDR2 is read until the quantity of receive data in SCFRDR2 becomes
less than the specified number of receive triggers by the DMAC, the RDF flag is read as 1, then 0
is written to the RDF flag.
When the ER flag in SCSSR2 is set to 1, an ERI interrupt request is generated.
When the BRK flag in SCSSR2 is set to 1, a BRI interrupt request is generated.
The TXI interrupt indicates that transmit data can be written, and the RXI interrupt indicates that
there is receive data in SCFRDR2.
Table 16.9 SCIF Interrupt Sources
Interrupt
Source
ERI
RXI
BRI
TXI
Description
DMAC
Activation
Interrupt initiated by receive error flag (ER)
Not possible
Interrupt initiated by receive data FIFO full flag
(RDF) or data ready flag (DR)
Possible
(RDF only)
Interrupt initiated by break flag (BRK)
Not possible
Interrupt initiated by transmit FIFO data empty flag Possible
(TDFE)
Priority on
Reset Release
High
Low
See section 4, Exception Processing, for priorities and the relationship with non-SCIF interrupts.
Rev. 5.00 May 29, 2006 page 480 of 698
REJ09B0146-0500