SH7706 Datasheet, PDF (621/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

22.3 Operation
Section 22 Power-Down Modes
22.3.1 Sleep Mode
Transition to Sleep Mode
Executing the SLEEP instruction when the STBY bit in STBCR is 0 causes a transition from the
program execution state to sleep mode. Although the CPU halts immediately after executing the
SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip supporting
modules continue to run during sleep mode and the clock continues to be output to the CKIO pin.
In sleep mode, the STATUS1 pin is set high and the STATUS0 pin low.
Canceling Sleep Mode
Sleep mode is canceled by an interrupt (NMI, IRQ, IRL, on-chip supporting module) or reset.
Interrupts are accepted during sleep mode even when the BL bit in the SR register is 1. If
necessary, save SPC and SSR in the stack before executing the SLEEP instruction.
Canceling with an Interrupt: When an NMI, IRQ, IRL or on-chip supporting module interrupt
occurs, sleep mode is canceled and interrupt exception processing is executed. A code indicating
the interrupt source is set in the INTEVT and INTEVT2 registers.
Canceling with a Reset: Sleep mode is canceled by a power-on reset or a manual reset.
Rev. 5.00 May 29, 2006 page 573 of 698
REJ09B0146-0500