SH7706 Datasheet, PDF (162/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 6 Interrupt Controller (INTC)
Figure 6.1 is a block diagram of the INTC.
IRQOUT
NMI
IRL3 to IRL0
IRQ0 to IRQ5
DMAC
SCIF
SCI
ADC
TMU
RTC
WDT
REF
H-UDI
Input
4
control
6
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request/
refresh request)
(Interrupt request)
Priority
identifier
Com-
parator
IPR
ICR
IPRA to IPRE
Legend:
TMU:
Timer unit
RTC:
Realtime clock unit
SCI:
Serial communication interface
SCIF:
Serial communication interface (with FIFO)
WDT:
Watchdog timer
REF:
Refresh requests in the bus state controller
ICR:
Interrupt control register
IPRA-IPRE: Registers A-E for setting the interrupt proprity levels
SR:
Status register
DMAC: Direct memory access controller
ADC:
Analog-to-digital converter
H-UDI:
User debugging interface
Bus
interface
INTC
Figure 6.1 INTC Block Diagram
Interrupt
request
SR
3210
CPU
Rev. 5.00 May 29, 2006 page 114 of 698
REJ09B0146-0500