SH7706 Datasheet, PDF (473/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 15 Smart Card Interface
15.3.2 Serial Status Register (SCSSR)
In the smart card interface mode, the function of bit 4 in SCSSR of the SCI is changed as shown
blow. Relating to this, the setting conditions for bit 2, the TEND bit, are also changed.
Bit
Bit Name Initial Value R/W Description
7
TDRE
1
R/(W)* Transmit Data Register Empty
6
RDRF
0
R/(W)* Receive Register Full
5
ORER
0
R/(W)* Overrun Error
These bits have the same function as in the ordinary
SCI. See section 14, Serial Communication Interface
(SCI), for more information.
4
ERS
0
R/(W)* Error Signal Status
In the smart card interface mode, bit 4 indicates the
state of the error signal returned from the receiving
side during transmission. The smart card interface
cannot detect framing errors.
0: Receiving ended normally with no error signal.
[Clearing conditions]
1. The chip is reset or enters standby mode.
2. ERS is read as 1, then written to with 0.
1: An error signal indicating a parity error was
transmitted from the receiving side.
[Setting condition]
The error signal sampled is low.
Note: The ERS flag maintains its state even when
the TE bit in SCSCR is cleared to 0.
Rev. 5.00 May 29, 2006 page 425 of 698
REJ09B0146-0500