SH7706 Datasheet, PDF (305/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 9 Direct Memory Access Controller (DMAC)
Bit
31 to
21
20
19
18
Bit Name
—
DI
RO
RL
Initial Value
All 0
0
0
0
R/W
R
(R/W)^*2
(R/W)^*2
(R/W)^*2
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Direct/Indirect Selection
DI selects direct address mode or indirect address
mode in channel 3.
This bit is only valid in CHCR_3 and is not used in
CHCR_0 to CHCR_2. Writing to this bit is invalid
in CHCR_0 to CHCR_2; 0 is read if this bit is
read. When using 16-byte transfer, direct address
mode must be specified. Operation is not
guaranteed if indirect address mode is specified.
0: Direct address mode
1: Indirect address mode
Source Address Reload
RO selects whether the source address initial
value is reloaded in channel 2.
This bit is only valid in CHCR_2 and is not used in
CHCR_0 to CHCR_1, or CHCR_3. Writing to this
bit is invalid in CHCR_0, CHCR_1, and CHCR_3;
0 is read if this bit is read. When using 16-byte
transfer, this bit must be cleared to 0, specifying
non-reloading. Operation is not guaranteed if
reloading is specified.
0: A source address is not reloaded
1: A source address is reloaded
Request Check Level
RL specifies the DRAK (acknowledge of DREQ)
signal output is high active or low active.
This bit is only valid in CHCR_0 and CHCR_1.
Writing to this bit is invalid in CHCR_2 and
CHCR_3; 0 is read if this bit is read.
0: Low-active output of DRAK
1: High-active output of DRAK
Rev. 5.00 May 29, 2006 page 257 of 698
REJ09B0146-0500