SH7706 Datasheet, PDF(77/749 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

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SH7706 Datasheet, PDF (77/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

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Section 2 CPU

Instruction Format

Source

Operand

Destination

Operand

Instruction

Example

nmd

format

15

0 mmmm: register

xxxx nnnn mmmm dddd direct

nnnndddd:

register indirect

with

displacement

MOV.L

Rm,@(disp,Rn)

mmmmdddd:

nnnn: register

register indirect direct

with displacement

MOV.L

@(disp,Rm),Rn

d format 15

0 dddddddd: GBR

xxxx xxxx dddd dddd indirect with

displacement

R0 (register

direct)

MOV.L

@(disp,GBR),R0

R0 (register direct) dddddddd: GBR MOV.L

indirect with R0,@(disp,GBR)

displacement

dddddddd:

PC-relative with

displacement

R0 (register

direct)

MOVA

@(disp,PC),R0

dddddddd:

â

PC-relative

BF

label

d12

15

0 dddddddddddd: â

format

xxxx dddd dddd dddd PC-relative

BRA label

(label = disp +

PC)

nd8

format

15

xxxx

nnnn

dddd

0 dddddddd:

dddd PC-relative with

displacement

nnnn: register MOV.L

direct

@(disp,PC),Rn

i format 15

0 iiiiiiii: immediate

xxxx xxxx i i i i i i i i

Indexed GBR

indirect

AND.B

#imm,

@(R0,GBR)

iiiiiiii: immediate

R0 (register

direct)

AND

#imm,R0

iiiiiiii: immediate â

TRAPA #imm

ni format 15

0 iiiiiiii: immediate

xxxx nnnn i i i i i i i i

nnnn: register ADD

direct

#imm,Rn

Note: * In a multiply-and-accumulate instruction, nnnn is the source register.

Rev. 5.00 May 29, 2006 page 29 of 698

REJ09B0146-0500

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