SH7706 Datasheet, PDF (515/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
Initial
Bit Bit Name Value R/W Description
2
TFRST
0
R/W Transmit FIFO Data Register Reset
Cancels the transmit data in the SCFTDR2 and resets the
data to the empty state.
0: Disables reset operation*
1: Enables reset operation
Note: * The reset is executed in a hardware reset or the
standby mode.
1
RFRST 0
R/W Receive FIFO Data Register Reset
Cancels the receive data in the SCFRDR2 and resets the
data to the empty state.
0: Disables reset operation*
1: Enables reset operation
Note: * The reset is executed in a hardware reset or the
standby mode.
0
LOOP
0
R/W Loop Back Test
Internally connects the transmit output pin (TXD2) and
receive input pin (RXD2) and enables the loop back test.
0: Disables the loop back test
1: Enables the loop back test
Rev. 5.00 May 29, 2006 page 467 of 698
REJ09B0146-0500