SH7706 Datasheet, PDF (324/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 9 Direct Memory Access Controller (DMAC)
(2) In the indirect address transfer mode, the address of memory in which data to be transferred
is stored is specified in the transfer source address register (SAR_3) in the DMAC. In this
mode, the address value specified in the transfer source address register in the DMAC is
read first. This value is temporarily stored in the DMAC. Next, the read value is output as
an address, and the value stored in that address is stored in the DMAC again. Then, the
value read afterwards is written to the address specified in the transfer destination address;
this completes one DMA transfer. 16-byte transfer is not possible.
Figure 9.9 shows one example. In this example, the transfer destination, the transfer source,
and the storage destination of the indirect address are external memories with a 16-bit
width in the indirect address mode, and transfer data is 16 or 8 bits. Figure 9.10 shows an
example of the transfer timing.
Rev. 5.00 May 29, 2006 page 276 of 698
REJ09B0146-0500