SH7706 Datasheet, PDF (620/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 22 Power-Down Modes
Bit
Bit Name Initial Value R/W
3
MSTP6 0
R/W
2
MSTP5 0
R/W
1
MSTP4 0
R/W
0
—
0
R
Description
Module Stop 6
Specifies halting of clock supply to the DAC (an
on-chip peripheral module). When the MSTP6 bit
is set to 1, the supply of the clock to the DAC is
halted.
0: DAC runs
1: Clock supply to DAC halted
Module Stop 5
Specifies halting of clock supply to the ADC (an
on-chip peripheral module). When the MSTP5 bit
is set to 1, the supply of the clock to the ADC is
halted and all registers are initialized.
0: ADC runs
1: Clock supply to ADC halted and all registers
initialized
Module Stop 4
Specifies halting the clock supply to the serial
communication interface with FIFO (an on-chip
peripheral module). When the MSTP1 bit is set to
1, the supply of the clock to the SCIF is halted.
0: SCIF runs
1: Clock supply to SCIF halted
Reserved
This bit is always read as 0. The write value
should always be 0.
Rev. 5.00 May 29, 2006 page 572 of 698
REJ09B0146-0500