SH7706 Datasheet, PDF (367/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 11 Watchdog Timer (WDT)
WTCNT write
15
Address: H'FFFFFF84
H'5A
87
0
Write data
WTCSR write
15
Address: H'FFFFFF86
H'A5
87
0
Write data
Figure 11.2 Writing to WTCNT and WTCSR
11.3 Operation
11.3.1 Canceling Software Standbys
The WDT can be used to cancel software standby mode with an NMI or other interrupts. The
procedure is described below. (The WDT does not run when resets are used for canceling, so keep
the RESETP pin or RESETM pin low until the clock stabilizes.)
1. Before transitioning to software standby mode, always clear the TME bit in WTCSR to 0.
When the TME bit is 1, an erroneous reset or interval timer interrupt may be generated when
the count overflows.
2. Set the type of count clock used in the CKS2 to CKS0 bits in WTCSR and the initial values for
the counter in the WTCNT counter. These values should ensure that the time till count
overflow is longer than the clock oscillation settling time.
3. Move to software standby mode by executing a SLEEP instruction to stop the clock.
4. The WDT starts counting by detecting the edge change of the NMI signal or detecting
interrupts.
5. When the WDT count overflows, the CPG starts supplying the clock and the processor
resumes operation. The WOVF flag in WTCSR is not set when this happens.
6. Since the WDT continues counting from H'00, set the STBY bit in the STBCR register to 0 in
the interrupt processing program and this will stop the WDT. When the STBY bit remains 1,
the SH7706 again enters the standby mode when the WDT has counted up to H'80. This
standby mode can be canceled by power-on resets.
Rev. 5.00 May 29, 2006 page 319 of 698
REJ09B0146-0500