SH7706 Datasheet, PDF (221/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 8 Bus State Controller (BSC)
IC Memory Card Interface
Pin Signal I/O Function
60 RFU
Reserved
61 REG
I Attribute memory
space select
62 BVD2
O Battery voltage
detection
63 BVD1
O Battery voltage
detection
64 D8
I/O Data
65 D9
I/O Data
66 D10
I/O Data
67 CD2
O Card detection
68 GND
Ground
Note: * This LSI does not support WP.
I/O Card Interface
Signal I/O Function
SH7706 Pin
INPACK O Input acknowledge —
REG
I Attribute memory —
space select
SPKR O Digital voice signal —
STSCHG O Card state
—
change
D8
I/O Data
D8
D9
I/O Data
D9
D10
I/O Data
D10
CD2
O Card detection
—
GND
Ground
—
8.4 Register Description
The BSC has 11 registers. The synchronous DRAM also has a built-in synchronous DRAM mode
register. These registers control direct connection interfaces to memory, wait states and refreshes.
Refer to section 23, List of Registers, for more details of the addresses and access sizes.
• Bus control register 1 (BCR1)
• Bus control register 2 (BCR2)
• Wait state control register 1 (WCR1)
• Wait state control register 2 (WCR2)
• Individual memory control register (MCR)
• PCMCIA control register (PCR)
• Synchronous DRAM mode register (SDMR)
• Refresh timer control/status register (RTCSR)
• Refresh timer counter (RTCNT)
• Refresh time constant register (RTCOR)
• Refresh count register (RFCR)
Rev. 5.00 May 29, 2006 page 173 of 698
REJ09B0146-0500