SH7706 Datasheet, PDF (179/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 6 Interrupt Controller (INTC)
6.4.5 Interrupt Request Register 1 (IRR1)
The interrupt request register 1 (IRR1) is an 8-bit read-only register that indicates whether DMAC
or IrDA interrupt requests are generated.
Bit
7 to 4
3
2
1
0
Bit Name Initial Value R/W Description
—
All 0
R Reserved
These bits are always read as 0. The write value should
always be 0.
DEI3R 0
R DEI3 Interrupt Request
Indicates whether a DEI3 (DMAC) interrupt request is
generated.
0: A DEI3 interrupt request is not generated
1: A DEI3 interrupt request is generated
DEI2R 0
R DEI2 Interrupt Request
Indicates whether a DEI2 (DMAC) interrupt request is
generated.
0: A DEI2 interrupt request is not generated
1: A DEI2 interrupt request is generated
DEI1R 0
R DEI1 Interrupt Request
Indicates whether a DEI1 (DMAC) interrupt request is
generated.
0: A DEI1 interrupt request is not generated
1: A DEI1 interrupt request is generated
DEI0R 0
R DEI0 Interrupt Request
Indicates whether a DEI0 (DMAC) interrupt request is
generated.
0: A DEI0 interrupt request is not generated
1: A DEI0 interrupt request is generated
Rev. 5.00 May 29, 2006 page 131 of 698
REJ09B0146-0500