SH7706 Datasheet, PDF (323/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 9 Direct Memory Access Controller (DMAC)
CKIO
A25 to A0
CSn
Transfer
+4
source address
+8
+12
Transfer
+4
destination address
+8
+12
D31 to D0
RD
WEn
DACKn
Data read cycle
(1st cycle)
(2nd cycle)
Note: Transfer between external memories, DACK output in a read cycle DACK output timing
is the same as that of CSn.
Figure 9.7 Example of DMA Transfer Timing in the Direct Address Mode
in the Dual Address Mode (16-Byte Transfer, Transfer Source: Ordinary Memory,
Transfer Destination: Ordinary Memory)
CKIO
A25 to A0
+4
Transfer source address
Transfer destination address
+8
+12
CSn
D31 to D0
RAS
CAS
RD/WR
WEn
DACKn
Data read cycle
(1st cycle)
(2nd cycle)
Data write cycle
Note: Transfer between external memories, DACK output in a read cycle DACK output timing
is the same as that of CSn.
Figure 9.8 Example of DMA Transfer Timing in the Direct Address Mode
in the Dual Address Mode (16-Byte Transfer, Transfer Source: Synchronous DRAM,
Transfer Destination: Ordinary Memory)
Rev. 5.00 May 29, 2006 page 275 of 698
REJ09B0146-0500