SH7706 Datasheet, PDF (193/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 7 User Break Controller
7.2.7 Break Data Mask Register B (BDMRB)
BDMRB is a 32-bit read/write register. BDMRB specifies bits masked in the break data specified
by BDRB.
Bit
Bit Name Initial Value R/W Description
31 to 0 BDMB31 to All 0
BDMB0
R/W Break Data Mask
0: Break data BDBn of channel B is included in the
break condition
1: Break data BDBn of channel B is masked and is
not included in the break condition
Notes: n = 31 to 0
Specify an operand size when including the value of the data bus in the break condition.
When a byte size is selected as a break condition, the break data must be set in bits 15 to 8
in BDRB for an even break address and bits 7 to 0 for an odd break address.
7.2.8 Break Bus Cycle Register B (BBRB)
Break bus cycle register B (BBRB) is a 16-bit read/write register, which specifies, (1) CPU cycle
or DMAC cycle, (2) instruction fetch or data access, (3) read/write, and (4) operand size in the
break conditions of channel B.
Bit
15 to 8
7
6
Bit Name
—
CDB1
CDB0
Initial Value R/W
All 0
R
0
R/W
0
R/W
Description
Reserved
These bits are always read as 0. These bits are
always read as 0.
CPU Cycle/DMAC Cycle Select B
Select the CPU cycle or DMAC cycle as the bus
cycle of the channel B break condition.
00: Condition comparison is not performed
X1: The break condition is the CPU cycle
10: The break condition is the DMAC cycle
Rev. 5.00 May 29, 2006 page 145 of 698
REJ09B0146-0500