SH7706 Datasheet, PDF (266/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 8 Bus State Controller (BSC)
Single Read
Figure 8.15 shows the timing when a single address read is performed. As the burst length is set to
1 in synchronous DRAM burst read/single write mode, only the required data is output.
Consequently, no unnecessary bus cycles are generated even when a cache-through area is
accessed.
CKIO
Address
upper bits
A12 or A11^*1
Address
lower bits^*2
CS2 or CS3
Tr
Tc1
Td1
Tpc
RASx
CASx
RD/WR
DQMxx
D31 to D0
BS
Notes: 1. Command bit
2. Column address
Figure 8.15 Basic Timing for Synchronous DRAM Single Read
Burst Write
The timing chart for a burst write is shown in figure 8.16. In this LSI, a burst write occurs only in
the event of cache write-back or 16-byte transfer by DMAC. In a burst write operation, following
the Tr cycle in which ACTV command output is performed, a WRIT command is issued in the
Rev. 5.00 May 29, 2006 page 218 of 698
REJ09B0146-0500