SH7706 Datasheet, PDF(144/749 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

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SH7706 Datasheet, PDF (144/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

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Section 4 Exception Processing

â¢ IRL Interrupts

ï£§ Conditions: The value of the interrupt mask bits in SR is lower than the IRL3 to IRL0 level

and the BL bit in SR is 0. The interrupt is accepted at an instruction boundary.

ï£§ Operations: The PC after the instruction that accepts the interrupt is saved to the SPC. SR

at the time the interrupt is accepted is saved to SSR. The code corresponding to the

IRL3 to IRL0 level is set in INTEVT and INTEVT2. The corresponding code is given as

H'200 + B' (IRL3âIRL0) Ã H'20. See table 6.4 for the corresponding code. The BL, MD,

and RB bits in SR are set to 1 and a branch occurs to VBR + H'0600. The received level is

not set in the interrupt mask bit of SR. See section 6, Interrupt Controller (INTC), for more

information.

â¢ IRQ Pin Interrupts

ï£§ Conditions: IRQ pin is asserted and the interrupt mask bit of SR is lower than the IRQ

priority level and the BL bit in SR is 0. The interrupt is accepted at an instruction

boundary.

ï£§ Operations: The PC after the instruction that accepts the interrupt is saved to the SPC. The

SR at the point the interrupt is accepted is saved to the SSR. The code corresponding to the

interrupt source is set to INTEVT and INTEVT2. The BL, MD, and RB bits of the SR are

set to 1 and a branch occurs to VBR + H'0600. The received level is not set to the interrupt

mask bit of SR. See section 6, Interrupt Controller (INTC), for more information.

â¢ On-Chip Peripheral Module Interrupts

ï£§ Conditions: The interrupt mask bit of SR is lower than the on-chip peripheral module

(TMU, RTC, SCI0, SCI2, A/D, LCDC, PCC, DMAC, WDT, REF) interrupt level and the

BL bit in SR is 0. The interrupt is accepted at an instruction boundary.

ï£§ Operations: The PC after the instruction that accepts the interrupt is saved to the SPC. The

SR at the point the interrupt is accepted is saved to the SSR. The code corresponding to the

interrupt source is set to INTEVT and INTEVT2. The BL, MD, and RB bits of the SR are

set to 1 and a branch occurs to VBR + H'0600. See section 6, Interrupt Controller (INTC),

for more information.

â¢ H-UDI Interrupt

ï£§ Conditions: H-UDI interrupt command is input (see section 21.4.4, H-UDI Interrupt) and

the interrupt mask bit of SR is lower than 15 and the BL bit in SR is 0. The interrupt is

accepted at an instruction boundary.

ï£§ Operations: The PC after the instruction that accepts the interrupt is saved to the SPC. The

SR at the point the interrupt is accepted is saved to the SSR. H'5E0 is set to INTEVT and

INTEVT2. The BL, MD, and RB bits of the SR are set to 1 and a branch occurs to VBR +

H'0600. See section 6, Interrupt Controller (INTC), for more information.

Rev. 5.00 May 29, 2006 page 96 of 698

REJ09B0146-0500

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