SH7706 Datasheet, PDF (520/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
Initialization
Clear TE and RE bits in SCSCR2 to 0
Set TFRST and RFRST bits in
SCFCR2 to 1
Set CKE1 and CKE0
bits in SCSCR2 (leaving TE and RE
bits cleared to 0)
Set data transfer format in SCSMR2
Set value in SCBRR2
Wait
No
1-bit interval elapsed?
Yes
Set RTRG1-0, TTRG1-0, and MCE
in SCFCR2
Clear TFRST and RFRST bits to 0
1. Set the clock selection in SCSCR2.
Be sure to clear bits RIE TIE, TE, and RE
to 0.
When clock output is selected, it is output
immediately after SCSCR2 settings are made.
2. Set the data transfer format in SCSMR2.
3. Write a value corresponding to the SCBRR2.
(Not necessary if an external clock is used.)
4. Wait at least one bit interval, then set the
TE bit or RE bit in SCSR2 to 1. Also set the
RIE and TIE bits.
Setting the TE and RE bits enables the
TxD2 and RxD2 pins to be used. When
transmitting, the SCIF will go to the mark
state; when receiving, it will go to the idle
state, waiting for a start bit.
Set TE and RE bits in
SCSCR2 to 1,and set RIE, TIE,
TEIE, and MPIE bits
End
Figure 16.5 Sample SCIF Initialization Flowchart
Rev. 5.00 May 29, 2006 page 472 of 698
REJ09B0146-0500