SH7706 Datasheet, PDF (216/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 8 Bus State Controller (BSC)
Table 8.2 Physical Address Space Map
Area Connectable Memory Physical Address
Capacity Access Size
0
Ordinary memory^*1, H'00000000 to H'03FFFFFF
64 Mbytes 8, 16, 32^*2
burst ROM
H'00000000 + H'20000000 × n to Shadow
H'03FFFFFF + H'20000000 × n
n: 1 to 6
1
Internal I/O registers^*8 H'04000000 to H'07FFFFFF
64 Mbytes 8, 16, 32^*3
H'04000000 + H'20000000 × n to Shadow
H'07FFFFFF + H'20000000 × n
n: 1 to 6
2
Ordinary memory^*1, H'08000000 to H'0BFFFFFF
64 Mbytes 8, 16, 32^{*3 *4}
synchronous DRAM
H'08000000 + H'20000000 × n to Shadow
H'0BFFFFFF + H'20000000 × n
n: 1 to 6
3
Ordinary memory^*1, H'0C000000 to H'0FFFFFFF
64 Mbytes 8, 16, 32^{*3 *5}
synchronous DRAM
H'0C000000 + H'20000000 × n to Shadow
H'0FFFFFFF + H'20000000 × n
n: 1 to 6
4
Ordinary memory^*1
H'10000000 to H'13FFFFFF
64 Mbytes 8, 16, 32^*3
H'10000000 + H'20000000 × n to Shadow
H'13FFFFFF + H'20000000 × n
n: 1 to 6
5
Ordinary memory^*1, H'14000000 to H'15FFFFFF
PCMCIA, burst ROM _{H'16000000 to H'17FFFFFF}
32 Mbytes
32 Mbytes
8, 16, 32^{*3 *6}
H'14000000 + H'20000000 × n to Shadow
H'17FFFFFF + H'20000000 × n
n: 1 to 6
6
Ordinary memory^*1, H'18000000 to H'19FFFFFF
PCMCIA, burst ROM _{H'1A000000 to H'1BFFFFFF}
32 Mbytes 8, 16, 32^{*3 *6}
7^*7 Reserved area
H'18000000 + H'20000000 × n to
H'1BFFFFFF + H'20000000 × n
H'1C000000 + H'20000000 × n
to H'1FFFFFFF + H'20000000 × n
Shadow
n: 1 to 6
n: 0 to 7
Notes: 1. Memory with interface such as SRAM or ROM.
2. Use external pin to specify memory bus width.
3. Use register to specify memory bus width.
4. With synchronous DRAM interfaces, bus width must be 16 or 32 bits.
5. With synchronous DRAM interfaces, bus width must be 16 or 32 bits.
6. With PCMCIA interface, bus width must be 8 or 16 bits.
7. Do not access the reserved area. If the reserved area is accessed, the correct
operation cannot be guaranteed.
8. When the control register in area 1 is not used for address translation by the MMU, set
the top three bits of the logical address to 101 to allocate in the P2 space.
Rev. 5.00 May 29, 2006 page 168 of 698
REJ09B0146-0500