SH7706 Datasheet, PDF (351/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 10 Clock Pulse Generator (CPG)
Section 10 Clock Pulse Generator (CPG)
The clock pulse generator (CPG) supplies all clocks to the processor and controls the power-down
modes. A block diagram of the clock pulse generator is shown in figure 10.1.
10.1 Feature
The CPG has the following features:
• Four clock modes: Selection of 4 clock modes for different frequency ranges, power
consumption, direct crystal input, and external clock input are available.
• Three clocks generated independently: An internal clock for the CPU, cache, and TLB (Iφ); a
peripheral clock (Pφ) for the on-chip supporting modules; and a bus clock (CKIO) for the
external bus interface.
• Frequency change function: CPU and peripheral clock frequencies can be changed
independently using the PLL circuit and divider circuit within the CPG. Frequencies are
changed by software using frequency control register (FRQCR) settings.
• Power-down mode control: The clock can be stopped for sleep mode and software standby
mode and specific modules can be stopped using the module standby function.
Rev. 5.00 May 29, 2006 page 303 of 698
REJ09B0146-0500