SH7706 Datasheet, PDF (476/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 15 Smart Card Interface
V_CC
TxD0
RxD0
SCK0
Px (port)
LSI
Connected device
Data line
Clock line
Reset line
IO
CLK
RST
IC card
Figure 15.2 Pin Connection Diagram for the Smart Card Interface
15.4.3 Data Format
Figure 15.3 shows the data format for the smart card interface. In this mode, parity is checked
every frame while receiving and error signals sent to the transmitting side whenever an error is
detected so that data can be re-transmitted. During transmission, if an error signal is sampled, the
same data is re-transmitted.
With no parity error
D_s D₀ D₁ D₂ D₃ D₄ D₅ D₆ D₇ D_p
Transmitting station output
With parity error
D_s D₀ D₁ D₂ D₃ D₄ D₅ D₆ D₇ D_p
D_E
Transmitting station output
Legend:
Ds:
Start bit
D0 to D7: Data bits
Dp:
Parity bit
DE:
Error signal
Receiving
station output
Figure 15.3 Data Format for Smart Card Interface
Rev. 5.00 May 29, 2006 page 428 of 698
REJ09B0146-0500