SH7706 Datasheet, PDF (135/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 4 Exception Processing
If the SPC and SSR have been saved in the external memory, set the BL bit in SR to 1, then
restore the SPC and SSR, and issue an RTE instruction.
4.2 Register Description
There are four registers related to exception processing. These are peripheral module registers, and
therefore reside in area P4. They can be accessed by specifying the address in the privileged mode
only.
There are following four registers related to exception processing. Registers with undefined initial
values (TRAPA exception register, Interrupt event register, and Interrupt event register 2) should
be initialized by software. Refer to section 23, List of Registers, for more details of the addresses
and access sizes.
• Exception event register (EXPEVT)
• Interrupt event register (INTEVT)
• Interrupt event register 2 (INTEVT2)
• TRAPA exception register (TRA)
4.2.1 Exception Event Register (EXPEVT)
The exception event register (EXPEVT) contains a 12-bit exception code. The exception code set
in EXPEVT is that for a reset or general exception event. The exception code is set automatically
by hardware when an exception occurs. EXPEVT can also be modified by software.
Bit
Bit Name
Initial Value R/W
Description
31 to 12 
All 0
R
Reserved
These bits are always read as 0. The
write value should always be 0.
11 to 0

*
R/W
12-bit exception code
Note: * H'0000 is set in a power-on reset, and H'020 in a manual reset.
Rev. 5.00 May 29, 2006 page 87 of 698
REJ09B0146-0500