SH7706 Datasheet, PDF (152/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 5 Cache
Table 5.3 Way to be Replaced when Cache Miss Occurs during Execution of Instruction
Other than PREF Instruction
CL bit W3LOAD W3LOCK W2LOAD W2LOCK Way to be Replaced
0
*
*
*
*
According to LRU (table 5.1)
1
*
0
*
0
According to LRU (table 5.1)
1
*
0
*
1
According to LRU (table 5.4)
1
*
1
*
0
According to LRU (table 5.5)
1
*
1
*
1
According to LRU (table 5.6)
Legend: * Don't care
Note: Do not set 1 into W2LOAD and W3LOAD at the same time.
Table 5.4 LRU and Way Replacement (When W2LOCK = 1)
LRU (5 to 0)
000000, 000001, 000100, 010100, 100000, 100001, 110000, 110100
000011, 000110, 000111, 001011, 001111, 010110, 011110, 011111
101001, 101011, 111000, 111001, 111011, 111100, 111110, 111111
Way to be Replaced
3
1
0
Table 5.5 LRU and Way Replacement (When W3LOCK = 1)
LRU (5 to 0)
000000, 000001, 000011, 001011, 100000, 100001, 101001, 101011
000100, 000110, 000111, 001111, 010100, 010110, 011110, 011111
110000, 110100, 111000, 111001, 111011, 111100, 111110, 111111
Way to be Replaced
2
1
0
Table 5.6 LRU and Way Replacement (When W2LOCK = 1 and W3LOCK = 1)
LRU (5 to 0)
000000, 000001, 000011, 000100, 000110, 000111, 001011, 001111,
010100, 010110, 011110, 011111
100000, 100001, 101001, 101011, 110000, 110100, 111000, 111001,
111011, 111100, 111110, 111111
Way to be Replaced
1
0
Rev. 5.00 May 29, 2006 page 104 of 698
REJ09B0146-0500