SH7706 Datasheet, PDF (592/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 19 A/D Converter (ADC)
*1
Pφ
Address
Write
signal
Input sampling
timing
ADF
*2
t_D
t_SPL
t_CONV
Legend:
t_D : A/D conversion start delay
t_SPL : Input sampling time
t_CONV : A/D conversion time
Notes: 1. ADCSR write cycle
2. ADCSR address
Figure 19.8 A/D Conversion Timing
Table 19.3 A/D Conversion Time (Single Mode)
CKS = 0
Symbol Min
Typ Max
Min
A/D conversion start t_D
delay
17
—
28
10
Input sampling time
t
SPL
—
129 —
—
A/D conversion time
t_CONV
514
—
525
259
Note: Values in the table are numbers of states (t_cyc).
CKS = 1
Typ
Max
—
17
65
—
—
266
Rev. 5.00 May 29, 2006 page 544 of 698
REJ09B0146-0500