SH7706 Datasheet, PDF (233/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Table 8.8 Area 4 Wait Control
Bit 9: A4W2
0
1
WCR2's bits
Bit 8: A4W1
0
1
0
1
Bit 7: A4W0
0
1
0
1
0
1
0
1
Section 8 Bus State Controller (BSC)
Description
Inserted Wait State WAIT Pin
0
Ignored
1
Enable
2
Enable
3
Enable
4
Enable
6
Enable
8
Enable
10
Enable
Table 8.9 Area 0 Wait Control
WCR2's bits
Bit 2: Bit 1: Bit 0:
A0W2 A0W1 A0W0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
Description
First Cycle
Burst Cycle
(Excluding First Cycle)
Inserted
Wait States
WAIT Pin
Number of States
Per Data Transfer WAIT Pin
0
Ignored
2
Enable
1
Enable
2
Enable
2
Enable
3
Enable
3
Enable
4
Enable
4
Enable
4
Enable
6
Enable
6
Enable
8
Enable
8
Enable
10
Enable
10
Enable
Rev. 5.00 May 29, 2006 page 185 of 698
REJ09B0146-0500