SH7706 Datasheet, PDF (169/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 6 Interrupt Controller (INTC)
Table 6.4 Interrupt Exception Handling Sources and Priority (IRL Mode)
Interrupt Source
NMI
H-UDI
IRL
IRL(3:0) = 0000
IRL(3:0) = 0001
IRL(3:0) = 0010
IRL(3:0) = 0011
IRL(3:0) = 0100
IRL(3:0) = 0101
IRL(3:0) = 0110
IRL(3:0) = 0111
IRL(3:0) = 1000
IRL(3:0) = 1001
IRL(3:0) = 1010
IRL(3:0) = 1011
IRL(3:0) = 1100
IRL(3:0) = 1101
IRL(3:0) = 1110
IRQ
IRQ4
IRQ5
DMAC DEI0
DEI1
DEI2
DEI3
SCIF ERI2
(SCI2) _RXI2
BRI2
TXI2
ADC ADI
INTEVT Code
(INTEVT2 Code)
Interrupt
Priority
IPR (Bit
(Initial Value) Numbers)
Priority
within IPR Default
Setting Unit Priority
H'1C0 (H'1C0)
16
—
—
High
H'5E0 (H'5E0)
15
—
—
H'200 (H'200)
15
—
—
H'220 (H'220)
14
—
—
H'240 (H'240)
13
—
—
H'260 (H'260)
12
—
—
H'280 (H'280)
11
—
—
H'2A0 (H'2A0)
10
—
—
H'2C0 (H'2C0)
9
—
—
H'2E0 (H'2E0)
8
—
—
H'300 (H'300)
7
—
—
H'320 (H'320)
6
—
—
H'340 (H'340)
5
—
—
H'360 (H'360)
4
—
—
H'380 (H'380)
3
—
—
H'3A0 (H'3A0)
2
—
—
H'3C0 (H'3C0)
1
—
—
H'200 to 3C0* (H'680) 0 to 15 (0) IPRD (3 to 0) —
H'200 to 3C0* (H'6A0) 0 to 15 (0) IPRD (7 to 4) —
H'200 to 3C0* (H'800) 0 to 15 (0) IPRE (15 to 12) High
H'200 to 3C0* (H'820)
H'200 to 3C0* (H'840)
H'200 to 3C0* (H'860)
Low
H'200 to 3C0* (H'900) 0 to 15 (0) IPRE (7 to 4) High
H'200 to 3C0* (H'920)
H'200 to 3C0* (H'940)
H'200 to 3C0* (H'960)
Low
H'200 to 3C0* (H'980) 0 to 15 (0) IPRE (3 to 0) —
Low
Rev. 5.00 May 29, 2006 page 121 of 698
REJ09B0146-0500