SH7706 Datasheet, PDF (325/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 9 Direct Memory Access Controller (DMAC)
SAR_3
D
DAR_3
M
A _Temporary
C
buffer
Data
buffer
Memory
Transfer source module
Transfer destination
module
When the value in SAR_3 is an address, the memory data is read and the value is
stored in the temporary buffer. The value to be read must be 32 bits since it is used
for the address.
First and second bus cycles
SAR_3
D
DAR_3
M
A _Temporary
C
buffer
Data
buffer
Memory
Transfer source module
Transfer destination
module
When the value in the temporary buffer is an address, the data is read from the
transfer source module to the data buffer.
Third bus cycle
SAR_3
D
DAR_3
M
A _Temporary
C
buffer
Data
buffer
Memory
Transfer source module
Transfer destination
module
When the value in SAR_3 is an address, the value in the data buffer is written to the
transfer source module.
Fourth bus cycle
Note: The above description uses the memory, transfer source module, or transfer
destination module; in practice, any module can be connected in the addressing
space.
Figure 9.9 Operation in the Indirect Address mode in the Dual Address Mode
(When the External Memory Space Has a 16-Bit Width)
Rev. 5.00 May 29, 2006 page 277 of 698
REJ09B0146-0500