SH7706 Datasheet, PDF (340/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 9 Direct Memory Access Controller (DMAC)
9.5 Compare Match Timer (CMT)
DMAC has an on-chip compare match timer (CMT) to generate DMA transfer request. The CMT
has 16-bit counter. Figure 9.26 shows a CMT block diagram.
9.5.1 Feature
The CMT has the following features:
• Four types of counter input clock can be selected
 One of four internal clocks (Pφ/4, Pφ/8, Pφ/16, Pφ/64) can be selected.
• Generate DMA transfer request when compare match occurs.
Control circuit
Pφ/4 Pφ/8 Pφ/16 Pφ/64
Clock selection
CMT
Module bus
Bus
interface
Legend:
CMSTR: Compare match timer start register
CMCSR: Compare match timer control/status register
CMCOR: Compare match timer constant register
CMCNT: Compare match timer counter
Internal bus
Figure 9.26 CMT Block Diagram
Rev. 5.00 May 29, 2006 page 292 of 698
REJ09B0146-0500