SH7706 Datasheet, PDF (38/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

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Cycle-Steal Mode, Level Input (CPU Access: 2 Cycles)..................................... 286
Cycle-Steal Mode, Level Input (CPU Access: 3 Cycles)..................................... 286
Cycle-Steal Mode, Level input
(CPU Access: 2 Cycles, DMA RD Access: 4 Cycles) ......................................... 286
Cycle-Steal Mode, Level input (CPU Access: 2 Cycles, DREQ Input Delayed) 287
Cycle-Steal Mode, Edge input (CPU Access: 2 Cycles)...................................... 287
Burst Mode, Level Input ...................................................................................... 287
Burst Mode, Edge Input....................................................................................... 288
Source Address Reload Function Diagram .......................................................... 288
Timing Chart of Source Address Reload Function .............................................. 289
CMT Block Diagram ........................................................................................... 292
Counter Operation................................................................................................ 295
Count Timing....................................................................................................... 296
CMF Set Timing .................................................................................................. 297
Timing of CMF Clear by the CPU....................................................................... 297
Section 10 Clock Pulse Generator (CPG)
Figure 10.1 Block Diagram of Clock Pulse Generator............................................................ 304
Figure 10.2 Points for Attention when Using Crystal Oscillator............................................. 313
Figure 10.3 Points for Attention when Using PLL Oscillator Circuit ..................................... 314
Section 11 Watchdog Timer (WDT)
Figure 11.1 Block Diagram of the WDT................................................................................. 315
Figure 11.2 Writing to WTCNT and WTCSR ........................................................................ 319
Section 12 Timer Unit (TMU)
Figure 12.1 TMU Block Diagram ........................................................................................... 324
Figure 12.2 Setting the Count Operation................................................................................. 333
Figure 12.3 Auto-Reload Count Operation ............................................................................. 334
Figure 12.4 Count Timing when Internal Clock Is Operating................................................. 334
Figure 12.5 Count Timing when External Clock Is Operating (Both Edges Detected)........... 335
Figure 12.6 Count Timing when On-Chip RTC Clock Is Operating ...................................... 335
Figure 12.7 Operation Timing when Using the Input Capture Function
(Using TCLK Rising Edge) ................................................................................. 336
Figure 12.8 UNF Set Timing................................................................................................... 337
Figure 12.9 Status Flag Clear Timing ..................................................................................... 337
Section 13 Realtime Clock (RTC)
Figure 13.1 RTC Block Diagram ............................................................................................ 340
Figure 13.2(a) Setting the Time................................................................................................... 357
Figure 13.2(b) Setting the Time................................................................................................... 357
Rev. 5.00 May 29, 2006 page xxxviii of xlviii