SH7706 Datasheet, PDF (301/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 9 Direct Memory Access Controller (DMAC)
On-chip
peripheral
module
DREQ0, DREQ1
SCIF
A/D converter
CMT
DEI_n
DACK0, DACK1
DRAK0, DRAK1
External
ROM
External
RAM
External I/O
(memory
mapped)
External I/O
(with
acknowledge)
Interation
control
DMAC module
SAR_n
Register
control
Start-up
control
DAR_n
DMATCR_n
CHCR_n
Request
priority
control
DMAOR
Bus interface
Bus state
controller
Legend:
DMAOR: DMAC operation register
SAR_n: DMAC source address register
DAR_n: DMAC destination address register
DMATCR_n: DMAC transfer count register
CHCR_n: DMAC channel control register
DEI_n:
DMA transfer-end interrupt request to CPU
Note: n: 0 to 3
Figure 9.1 DMAC Block Diagram
Rev. 5.00 May 29, 2006 page 253 of 698
REJ09B0146-0500