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| SH7706 Datasheet, PDF (672/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series | |||
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Section 24 Electrical Characteristics
24.3.4 Basic Timing
T1
T2
CKIO
A25 to A0
tAD tAS
CSn
RD/WR
tCSD1
tRWD
RD
(read)
tRSD
D31 to D0
(read)
WEn
(write)
D31 to D0
(write)
BS
DACKn
tWED
tWDD1
tBSD
tDAKD1
tAD
tCSD2
tAH
tRWH
tRDH1
tRWD
tRSD
tAH
tRWH
tRDS1
tRDH1
tWED
tAH
tRWH
tWDH3
tWDH1
tBSD
tDAKD2
Note: tRDH1: Stipulated from the faster negate timing of CSn or RD
tAH: Stipulated from the slower negate timing of CSn, RD, or WEn
Figure 24.16 Basic Bus Cycle (No Wait)
Rev. 5.00 May 29, 2006 page 624 of 698
REJ09B0146-0500
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