SH7706 Datasheet, PDF (188/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 7 User Break Controller
Access
Control
IAB LAB
Access
comparator
Address
comparator
ASID
comparator
Channel A
BBRA
BARA
BAMRA
BASRA
MDB
Access
comparator
Address
comparator
ASID
comparator
Data
comparator
Channel B
PC Trace
CONTROL
BBRB
BARB
BAMRB
BASRB
BDRB
BDMRB
BETR
BRSR
BRDR
BRCR
LDB/IDB
CPU state
signals
User break request
UBC Location
CCN Location
Legend:
BBRA : Break bus cycle register A
BARA : Break address register A
BAMRA : Break address mask register A
BASRA : Break ASID register A
BBRB : Break bus cycle register B
BARB : Break address register B
BAMRB : Break address mask register B
BASRB : Break ASID register B
BDRB : Break data register B
BDMRB : Break data mask register B
BETR : Break execution times register
BRSR : Branch source register
BRDR : Branch destination register
BRCR : Break control register
Figure 7.1 Block Diagram of User Break Controller
Rev. 5.00 May 29, 2006 page 140 of 698
REJ09B0146-0500