SH7706 Datasheet, PDF (285/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 8 Bus State Controller (BSC)
Figure 8.31 shows an example of PCMCIA card connection to this LSI. To enable active insertion
of the PCMCIA cards (i.e. insertion or removal while system power is being supplied), a 3-state
buffer must be connected between this LSI bus interface and the PCMCIA cards.
As operation in big-endian mode is not explicitly stipulated in the JEIDA/PCMCIA specifications,
the PCMCIA interface for this LSI in big-endian mode is stipulated independently.
However, the WAIT signal is ignored in the following cases:
• In 16-byte DMA transfer or dual addressing mode, or when writing data to the external
address area
• In 16-byte DMA transfer or single addressing mode, or when transferring data from an
external device with DACK to the external bus area
• When accessing cache for write back
32-Mbyte capacity (REG = I/O port)
Area 5: H'14000000
Area 5: H'16000000
Area 6: H'18000000
Area 6: H'1A000000
Common memory/
attribute memory
I/O space
Common memory/
attribute memory
I/O space
Up to 16-Mbyte capacity (REG = A24)
Area 5: H'14000000
Area 5: H'15000000
Area 5: H'16000000
H'17000000
Area 6: H'18000000
Area 6: H'19000000
Area 6: H'1A000000
H'1B000000
Attribute memory
Common memory
I/O space
Attribute memory
Common memory
I/O space
Figure 8.30 PCMCIA Space Allocation
Rev. 5.00 May 29, 2006 page 237 of 698
REJ09B0146-0500