SH7706 Datasheet, PDF (416/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 14 Serial Communication Interface (SCI)
14.3.1 Receive Shift Register (SCRSR)
The receive shift register (SCRSR) is an 8-bit register that receives serial data. Data input at the
RxD pin is loaded into the SCRSR in the order received, LSB (bit 0) first, converting the data to
parallel form. When one byte has been received, it is automatically transferred to the SCRDR. The
CPU cannot read or write the SCRSR directly.
14.3.2 Receive Data Register (SCRDR)
The receive data register (SCRDR) is an 8-bit register that stores serial receive data. The SCI
completes the reception of one byte of serial data by moving the received data from the SCRSR
into the SCRDR for storage. The SCRSR is then ready to receive the next data. This double
buffering allows the SCI to receive data continuously.
The CPU can read but not write the SCRDR. The SCRDR is initialized to H'00 by a reset or in
standby or module standby modes.
14.3.3 Transmit Shift Register (SCTSR)
The transmit shift register (SCTSR) transmits serial data. The SCI loads transmit data from the
SCTDR into the SCTSR, then transmits the data serially to the TxD0 pin, LSB (bit 0) first. After
transmitting one-byte data, the SCI automatically loads the next transmit data from the SCTDR
into the SCTSR and starts transmitting again. If the TDRE bit of the SCSSR is 1, however, the
SCI does not load the SCTDR contents into the SCTSR. The CPU cannot read or write the SCTSR
directly.
14.3.4 Transmit Data Register (SCTDR)
The transmit data register (SCTDR) is an eight-bit register that stores data for serial transmission.
When the SCI detects that the SCTSR is empty, it moves transmit data written in the SCTDR into
the SCTSR and starts serial transmission. Continuous serial transmission is possible by writing the
next transmit data in the SCTDR during serial transmission from the SCTSR.
The CPU can always read and write the SCTDR. The SCTDR is initialized to H'FF by a reset or in
standby and module standby modes.
Rev. 5.00 May 29, 2006 page 368 of 698
REJ09B0146-0500