SH7706 Datasheet, PDF (276/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 8 Bus State Controller (BSC)
CKIO
Address
upper bits
A12 or A11^*1
Address
lower bits^*2
CS2 or CS3
RASx
CASx
RD/WR
DQMxx
D31 to D0
BS
Tp
Tr
Tc1
Tc2
Tc3
Td4
Notes: 1. Command bit
2. Column address
Figure 8.23 Burst Write Timing (Different Row Addresses)
Refreshing
The bus state controller is provided with a function for controlling synchronous DRAM
refreshing. Auto-refreshing can be performed by clearing the RMODE bit to 0 and setting the
RFSH bit to 1 in MCR. If synchronous DRAM is not accessed for a long period, self-refresh
mode, in which the power consumption for data retention is low, can be activated by setting both
the RMODE bit and the RFSH bit to 1.
Rev. 5.00 May 29, 2006 page 228 of 698
REJ09B0146-0500