SH7706 Datasheet, PDF (231/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 8 Bus State Controller (BSC)
Bit
Bit Name Initial Value R/W Description
4
A2W1
1
R/W Area 2 Wait Control
3
A2W0
1
R/W Specify the number of wait states inserted into
physical space area 2.
• For Ordinary memory
Inserted Wait States
00:
0
01:
1
10:
2
11:
3
WAIT Pin
Ignored
Enabled
Enabled
Enabled
2
A0W2
1
1
A0W1
1
0
A0W0
1
• For Synchronus DRAM
Synchronus DRAM: CAS Latency
00:
1
01:
1
10:
2
11:
3
R/W Area 0 Wait Control
R/W Specify the number of wait states inserted into
R/W ^{physical space area 0. Also specify the burst pitch for}
burst transfer.
Refer to table 8.9 for details.
Rev. 5.00 May 29, 2006 page 183 of 698
REJ09B0146-0500