SH7706 Datasheet, PDF (366/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 11 Watchdog Timer (WDT)
Bit
Bit Name Initial Value R/W Description
2 to 0 CKS2 to 0
CKS0
R/W Clock Select 2 to 0
These bits select the clock to be used for the WTCNT
count from the eight types obtainable by dividing the
peripheral clock. The overflow period in the table is
the value when the peripheral clock (Pφ) is 15 MHz.
Clock Division Ratio Overflow Period
(when Pφ = 15 MHz)
000: 1
17 µs
001: 1/4
010: 1/16
68 µs
273 µs
011: 1/32
546 µs
100: 1/64
1.09 ms
101: 1/256
4.36 ms
110: 1/1024
17.48 ms
111: 1/4096
69.91 ms
Note:
If bits CKS2 to CKS0 are modified when the
WDT is running, the up-count may not be
performed correctly. Ensure that these bits are
modified only when the WDT is not running.
Note: The watchdog timer control/status register (WTCSR) is more difficult to write to than other
registers to prevent from the erroneous writing to the register. Refer to 11.2.3, Notes on
Register Access.
11.2.3 Notes on Register Access
The WTCNT and WTCSR are more difficult to write to than other registers. The procedure for
writing to these registers are given below.
Writing to WTCNT and WTCSR: These registers must be written by a word transfer
instruction. They cannot be written by a byte or longword transfer instruction. When writing to
WTCNT, set the upper byte to H'5A and transfer the lower byte as the write data, as shown in
figure 11.2. When writing to WTCSR, set the upper byte to H'A5 and transfer the lower byte as
the write data. This transfer procedure writes the lower byte data to WTCNT or WTCSR.
Rev. 5.00 May 29, 2006 page 318 of 698
REJ09B0146-0500