SH7706 Datasheet, PDF (568/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 18 I/O Ports
18.7.2 Port G Data Register (PGDR)
Port G data register (PGDR) is an 8-bit read register that stores data for pins PTG5 to PTG0.
PG5DT to PG0DT bit corresponds to PTG5 to PTG0 pin. When the function is general input port,
if the port is read the corresponding pin level is read.
PGDR is initialized by a power-on reset, after which the general input port function (pull-up MOS
on) is set as the initial pin function, and the corresponding pin levels are read. It retains its
previous value in standby mode and sleep mode, and in a manual reset.
Bit
Bit Name Initial Value R/W
7

*
R
6

*
R
5
PG5DT *
R
4
PG4DT *
R
3
PG3DT *
R
2
PG2DT *
R
1
PG1DT *
R
0
PG0DT *
R
Legend: * Undefined
Description
Reserved
Table 18.7 shows the function of PGDR.
Table 18.7 Read/Write Operation of the Port G Data Register (PGDR)
PGnMD1 PGnMD0 Pin State
Read
0
0
Other function Low level
1
Reserved

1
0
Input (Pull-up Pin state
MOS: on)
1
Input (Pull-up Pin state
MOS: off)
Note: n = 0 to 5
Write
Ignored (no affect on pin state)
Ignored (no affect on pin state)
Ignored (no affect on pin state)
Ignored (no affect on pin state)
Rev. 5.00 May 29, 2006 page 520 of 698
REJ09B0146-0500