SH7706 Datasheet, PDF (161/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 6 Interrupt Controller (INTC)
Section 6 Interrupt Controller (INTC)
The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt
requests to the CPU. The INTC has registers for setting the priority of each interrupt, and interrupt
requests are handled according to the priorities set in these registers.
6.1 Feature
INTC has the following features:
• 16 levels of interrupt priority can be set: By setting the five interrupt-priority registers, the
priorities of on-chip peripheral module, IRQ interrupts can be selected from 16 levels for
individual request sources.
• NMI noise canceler function: NMI input-level bit indicates NMI pin states. By reading this bit
in the interrupt exception service routine, the pin state can be checked, enabling it to be used as
a noise canceler.
• External devices can be notified that an interrupt has been received (IRQOUT): When the
SH7706 has released the bus right, the external bus master can be notified that an external
interrupt, an on-chip peripheral module interrupt or a memory refresh request has occurred,
enabling this LSI to request the bus right.
Rev. 5.00 May 29, 2006 page 113 of 698
REJ09B0146-0500