SH7706 Datasheet, PDF (228/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 8 Bus State Controller (BSC)
Bit Bit Name Initial Value R/W Description
15
WAITSEL 0
R/W WAIT Sampling Timing Select
Specifies the WAIT signal sampling timing.
0: Set 1 to use the WAIT signal.
1: The WAIT signal is sampled at the falling edge of
CKIO.
14
—
0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
13
A6IW1
1
R/W Area 6 Intercycle Idle Specification
12
A6IW0
1
R/W Specify the number of idles inserted between bus
cycles when switching between physical space area
6 to another space or between a read access to a
write access in the same physical space.
00: 1 idle cycle inserted
01: 1 idle cycle inserted
10: 2 idle cycles inserted
11: 3 idle cycles inserted
11
A5IW1
1
R/W Area 5 Intercycle Idle Specification
10
A5IW0
1
R/W Specify the number of idles inserted between bus
cycles when switching between physical space area
5 to another space or between a read access to a
write access in the same physical space.
00: 1 idle cycle inserted
01: 1 idle cycle inserted
10: 2 idle cycles inserted
11: 3 idle cycles inserted
9
A4IW1
1
R/W Area 4 Intercycle Idle Specification
8
A4IW0
1
R/W Specify the number of idles inserted between bus
cycles when switching between physical space area
4 to another space or between a read access to a
write access in the same physical space.
00: 1 idle cycle inserted
01: 1 idle cycle inserted
10: 2 idle cycles inserted
11: 3 idle cycles inserted
Rev. 5.00 May 29, 2006 page 180 of 698
REJ09B0146-0500