SH7706 Datasheet, PDF (321/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 9 Direct Memory Access Controller (DMAC)
Address Modes:
• Dual Address Mode
In the dual address mode, both the transfer source and destination are accessed (selectable) by
an address. The source and destination can be located externally or internally. The dual address
mode has (1) direct address transfer mode and (2) indirect address transfer mode.
(1) In the direct address transfer mode, DMA transfer requires two bus cycles because data is
read from the transfer source in a data read cycle and written to the transfer destination in a
data write cycle. At this time, transfer data is temporarily stored in the DMAC. In the
transfer between external memories as shown in figure 9.5, data is read to the DMAC from
one external memory in a data read cycle, and then that data is written to the other external
memory in a write cycle. Figures 9.6 to 9.8 show examples of the timing at this time.
DMAC
SAR
DAR
Memory
Transfer source
module
Data buffer
Transfer destination
module
The SAR value is an address, data is read from the transfer source module,
and the data is tempolarily stored in the DMAC.
First bus cycle
DMAC
SAR
Memory
DAR
Transfer source
module
Data buffer
Transfer destination
module
The DAR value is an address and the value stored in the data buffer in the
DMAC is written to the transfer destination module.
Second bus cycle
Figure 9.5 Operation in the Direct Address Mode in the Dual Address Mode
Rev. 5.00 May 29, 2006 page 273 of 698
REJ09B0146-0500