SH7706 Datasheet, PDF (131/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 4 Exception Processing
Exception Current
Type
Instruction Exception Event
Exception Vector
Priority^*1 Order
Address
Vector
Offset
General Aborted
TLB protection violation 2
4
—
exception and retried (instruction access)
events
General illegal
2
5
—
instruction exception
H'00000100
H'00000100
Illegal slot
2
5
—
instruction exception
H'00000100
CPU Address error
2
6
—
(data access)
H'00000100
TLB miss
2
7
—
(data access not in
repeat loop)
H'00000400
TLB invalid (data
2
8
—
access)
H'00000100
TLB protection violation 2
9
—
(data access)
H'00000100
Initial page write
2
10
—
H'00000100
Completed Unconditional trap
2
(TRAPA instruction)
User breakpoint trap 2
5
—
n^*2
—
H'00000100
H'00000100
DMA address error
2
12
—
H'00000100
General Completed Nonmaskable interrupt 3
—
—
interrupt
requests
External hardware
4^*3
—
—
interrupt
H-UDI interrupt
4^*3
—
—
H'00000600
H'00000600
H'00000600
Notes: 1. Priorities are indicated from high to low, 1 being highest and 4 being lowest.
2. The user defines the break point traps. 1 is a break point before instruction execution
and 11 is a break point after instruction execution. For an operand break point, use 11.
3. Use software to specify relative priorities of external hardware interrupts and peripheral
module interrupts (see section 6, Interrupt Controller (INTC)).
4.1.3 Acceptance of Exceptions
Processor resets and interrupts are asynchronous events unrelated to the instruction stream. All
exception events are prioritized to establish an acceptance order whenever two or more exception
events occur simultaneously. If a power-on reset and manual reset occur simultaneously, the
power-on reset takes precedence.
Rev. 5.00 May 29, 2006 page 83 of 698
REJ09B0146-0500