SH7706 Datasheet, PDF (506/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
Initial
Bit Bit Name Value R/W Description
1
RDF
0
R/(W)* Receive FIFO Data Full
Indicates that received data is transferred to the
SCFRDR2, the quantity of data in SCFRDR becomes more
than the number of receive triggers specified by the
RTRG1 and RTRG0 bits in SCFCR2.
0: The quantity of transmit data written to SCFRDR2 is less
than the specified number of receive triggers.
[Clearing conditions]
1. The chip is power-on reset or enters standby mode.
2. When SCFRDR2 is read until the quantity of receive
data in SCFRDR2 becomes less than the specified
number of receive triggers, software reads RDF after
it has been set to 1, and then writes 0 to RDF.
1: The quantity of receive data in SCFRDR2 is more than
the specified number of receive triggers.
[Setting condition]
The quantity of receive data which is greater than the
specified number of receive triggers is being stored to
SCFRDR2.*
Note: * Since SCFTDR2 is a 16-byte FIFO register, the
maximum quantity of data which can be read when
RDF is 1 is the specified number of receive triggers.
If attempted to read after all data in the SCFRDR2
have been read, the data is undefined. The quantity
of receive data in SCFRDR2 is indicated by the
lower 8 bits of SCFTDR2.
Rev. 5.00 May 29, 2006 page 458 of 698
REJ09B0146-0500