SH7706 Datasheet, PDF (418/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 14 Serial Communication Interface (SCI)
Bit
Bit Name Initial Value R/W Description
4
O/E
0
R/W Parity Mode
Selects even or odd parity when parity bits are
added and checked. The O/E setting is available
only when the PE is set to 1 to enable parity
addition and check in asynchronous mode. The
O/E setting is ignored in the clock synchronous
mode, or in the asynchronous mode when parity
addition and check is disabled.
0: Even parity
Note: If even parity is selected, the parity bit is
added to transmit data to make an even number
of 1s in the transmitted character and parity bit.
Receive data is checked to see if it has an even
number of 1s in the received character and
parity bit combined.
1: Odd parity
Note: If odd parity is selected, the parity bit is
added to transmit data to make an odd number
of 1s in the transmitted character and parity bit.
Receive data is checked to see if it has an odd
number of 1s in the received character and
parity bit combined.
3
STOP
0
R/W Stop Bit Length
Selects one or two bits as the stop bit length in the
asynchronous mode. This setting is used only in
the asynchronous mode. It is ignored in the clock
synchronous mode because no stop bits are
added.
0: One stop bit
Note: In transmitting, a single bit of 1 is added
at the end of each transmitted character.
1: Two stop bits
Note: In transmitting, two bits of 1 are added at
the end of each transmitted character.
In receiving, only the first stop bit is checked,
regardless of the STOP bit setting. If the second
stop bit is 1, it is treated as a stop bit, but if the
second stop bit is 0, it is treated as the start bit of
the next incoming character.
Rev. 5.00 May 29, 2006 page 370 of 698
REJ09B0146-0500