SH7706 Datasheet, PDF (572/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 18 I/O Ports
18.9.2 Port J Data Register (PJDR)
Port J data register (PJDR) is an 8-bit read register that stores data for pins PTJ7 to PTJ0. PJ3DT
to PJ0DT bit corresponds to PTJ3 to PTJ0 pin. When the pin function is general output port, if the
port is read the value of the corresponding PJDR bit is returned directly. When the function is
general input port, if the port is read, the corresponding pin level is read.
Bit
Bit Name Initial Value R/W Description
7

0
R
Reserved
6

0
R
5

0
R
4

0
R
3
PJ3DT
0
R
Table 18.9 shows the function of PJDR.
2
PJ2DT
0
R
1
PJ1DT
0
R
0
PJ0DT
0
R
Table 18.9 Read/Write Operation of the Port J Data Register (PJDR)
PJnMD1 PJnMD0 Pin State
Read
0
0
Other function Low level
1
Reserved

(Setting
prohibited)
1
0
Input
Pin state
1
Input
Pin state
Note: n = 0 to 3
Write
Ignored (no affect on pin state)
Ignored (no affect on pin state)
Ignored (no affect on pin state)
Ignored (no affect on pin state)
Rev. 5.00 May 29, 2006 page 524 of 698
REJ09B0146-0500