SH7706 Datasheet, PDF (334/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 9 Direct Memory Access Controller (DMAC)
1st sampling
CKIO
DREQ
DRAK
(High active)
Bus cycle
DACK
CPU
2nd sampling
DMAC(Read)
3rd sampling
DMAC(Write)
CPU
DMAC(Read)
Figure 9.17 Cycle-Steal Mode, Level Input (CPU Access: 2 Cycles)
DMAC(Write)
1st sampling
CKIO
DREQ
DRAK
(High active)
Bus cycle
DACK
CPU
2nd sampling
DMAC(Read)
3rd sampling
DMAC(Write)
CPU
DMAC(Read)
Figure 9.18 Cycle-Steal Mode, Level Input (CPU Access: 3 Cycles)
1st sampling 2nd sampling
CKIO
DREQ
DRAK
(High active)
Bus cycle
DACK
(RD output)
CPU
DMAC(Read)
3rd sampling
DMAC(Write)
CPU
DMAC(Read)
Figure 9.19 Cycle-Steal Mode, Level input (CPU Access: 2 Cycles, DMA RD Access: 4
Cycles)
Rev. 5.00 May 29, 2006 page 286 of 698
REJ09B0146-0500